1. Field of the Invention
The technology relates to nonvolatile memory, and in particular, nonvolatile memory with a modified channel region interface, such as a raised source and drain or a recessed channel region.
2. Description of Prior Art
Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as EEPROM and flash memory are used in a variety of modem applications. A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry names PHINES, SONOS, or NROM, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer.
Conventional nonvolatile nitride cell structures are planar, such that the oxide-nitride-oxide (ONO) structure is formed on the surface of the substrate. However, such planar structures are associated with poor scalability, high power program and erase operations, and a high sheet resistance. Such a structure is described in YEH, C. C., et al., “PHINES: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory,” Electron Devices Meeting, 2002. IEDM '02. Digest. International, 8-11 Dec. 2002, Pages: 931-934.
Accordingly, it would be desirable to modify the planar structure of conventional nonvolatile nitride cell structures, to address one or more of these shortcomings.